Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 μm Technology

著者

  • Haresh P. Patani Department of VLSI, L. C. Institute of Technology, Bhandu, Gujarat, India
  • Nilesh D. Patel Department of VLSI, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

要旨

In this paper, “Development of High Impedance Current Mirror, based super wilson current mirror with both low input and output voltage requirements, along with high output impedance with no any extra biasing circuitry” is implemented. The implemented current mirror uses MOS current dividers to sample the output current to attain very high impedance with a large output and voltage range. A feedback action is used to force the input and output currents to be equal. The proposed circuit is also not sensitive to the biasing current. This achievement yields an increase in the output impedance by an aspect of about gmrout compared with that of the super-wilson current mirror. The implemented current mirror circuit was implemented using a TSMC-180 nm CMOS technology and simulated using by ‘Eldo Spice’, Design Architect and IC station of mentor graphics tool to validate its performance. The output current is mirrored with a transfer fault poorer than 1% when the input current is amplified from 5 μA–40 μA.   Keywords: Current mirror, Wilson current mirror, Output Impedance, Drain symmetry, Auxiliary current source Cite this Article Patani HP, Patel ND. Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 μm Technology. Journal of VLSI Design Tools and Technology. 2015; 5(3):     87–96p.

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発行日

2015-11-05

巻号

巻 5 号 3 (2015)

セクション

Research Articles

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