FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier

著者

  • Priyanka Rani Department of Electronics and Communication, Thapar University, Patiala, Punjab, India
  • Sakshi Bajaj Department of Electronics and Communication, Thapar University, India

要旨

This paper presents the hardware design of an IEEE P754-2008 complaint multiplier which works on binary integer decimal (BID) encoded decimal floating point numbers. This design uses a single binary multiplier with carry save feedback for both significant multiplication and rounding. It further uses the Dadda or Wallace tree structure to accumulate the partial products. In this design carry select adders, carry look ahead adders and ripple carry adders are used to compare their performance. Then their results in the terms of area and delay are compared for BID multiplier using different adders.   Keywords: Area, Binary integer decimal numbers, Decimal floating point numbers, Delay, IEEE P754-2008, Rounding Cite this Article Rani P, Bajaj S. FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier. Journal of VLSI Design Tools and Technology. 2015; 5(3): 97–103p.

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発行日

2015-11-05

巻号

巻 5 号 3 (2015)

セクション

Research Articles

ライセンス

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