Design and Implementation of Low Power 8-bit Level Crossing ADC

著者

  • Vaishali Gupta School of VLSI Design and Embedded Systems, National Institute of Technology, Kurukshetra, India
  • Anil Kumar Gupta School of VLSI Design and Embedded Systems, National Institute of Technology, Kurukshetra, India

要旨

Implantable medical devices, electronic gadgets, wireless communication elements and many other such applications require low power electronic circuits. Analog to digital converters are essential part of most of such circuits. This paper presents a design of the level crossing analog to digital converter (LC-ADC) architecture. The proposed circuit and layout has been implemented in semi-conductor laboratory (SCL) 180 nm technology and its performance was evaluated using cadence virtuoso at supply voltage 0.8 V. DRC, LVS and PEX were performed using calibre. The pre- and post-layout simulation results have been compared using Hspice circuit simulator. The proposed ADC consumes 90 nW-184nW power in frequency range 0.005-3KHz and takes up 0.025 mm2 silicon area.   Keywords: Analog to digital converter (ADC), level crossing, quantization, comparator, 1 bit digital to analog converter (DAC)Cite this Article Vaishali Gupta1 and Anil Kumar Gupta. Design and Implementation of Low Power 8-bit Level Crossing ADC. Journal of VLSI Design Tools and Technology. 2016; 6(2): 33–43p.

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発行日

2016-07-05

巻号

巻 6 号 2 (2016)

セクション

Research Articles

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