Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog

要旨

Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are: Productivity, Efficiency, Reusability and Completeness. About 75-80 % of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is System Verilog which is based on Object Oriented Programming concepts (OOPs). A design can be verified by writing a verification written in System Verilog. Basically SV can be used for both design and verification, so it is termed as Hardware Design and Verification Language (HDVL). The work embodied in this paper presents the verification of Advanced High Performance Bus-Lite (AHB-Lite), which is the subset of Advanced Microcontroller Bus Architecture (AMBA). The verification environment is created using System Verilog; and Functional Coverage is computed to ensure functional correctness of the design. The functional coverage was found to be 100%.