Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops

著者

  • Gunjankumar R. Modi Department of Electronics and Communication Engineering, L.C. Institute of Technology, Bhandu, Mehsana, Gujarat, India
  • Priyesh P. Gandhi Department of Electronics and Communication Engineering, L.C. Institute of Technology, Bhandu, Mehsana, Gujarat, India
  • Nilesh D. Patel Principal, M.L. Institute of Diploma Studies, Bhandu, Mehsana, Gujarat, India

要旨

This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. So, it is suitable for low power application.   Keywords: Dead zone, glitch period, phase-locked loops, phase frequency detectorCite this Article Gunjankumar R. Modi, Priyesh P. Gandhi, Nilesh D. Patel. Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops. Journal of VLSI Design Tools and Technology. 2017; 7(1): 18–28p.

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発行日

2017-03-23

巻号

巻 7 号 1 (2017)

セクション

Research Articles

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