Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology

著者

  • Rahulkumar S. Suthar Department of Electronics & Communication, L.C. Institute of Technology, Bhandu
  • Priyesh P. Gandhi Department of Electronics & Communication, L.C. Institute of Technology, Bhandu.

要旨

This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices.   Keywords: Folding ADC, interpolating, ADC, low power comparatorCite this Article Suthar Rahulkumar S, Gandhi Priyesh P. Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology. Journal of VLSI Design Tools & Technology. 2017; 7(1): 35–40p.

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発行日

2017-04-06

巻号

巻 7 号 1 (2017)

セクション

Research Articles

ライセンス

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