Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology

Resumo

In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze the rise time and settling time in similar analysis. The model evaluates the performance of a system which is expressed in terms of the transient response for the unit impulse input because it is easy to generate and evaluate the delay analytically. The transient response of a system to a unit impulse input depends upon the initial conditions. In this paper, a new interconnect model is presented; the model is based on the RLCG transmission line whose response is evaluated in time domain for a unit impulse input. In this model the delay is calculated in SPICE and MATLAB. No approximation is made to the transfer function of the interconnect. A closed form expression for the propagation delay of a CMOS gate driving a distributed RLCG line is introduced. On-chip inductance and conductance are shown to have a profound effect on the high performance IC design methodologies. In this proposed model we have shown that with the increase in the value of conductance by keeping constant the values of R, L, C we evaluate that the SPICE delay reduces but if we compare it with the MATLAB proposed delay model we see very accurately that the variation in the proposed delay is much larger in comparison to the SPICE delay. Hence, for a high-speed circuit, one must increase the value of G, so that the steady-state condition is reached as soon as possible. The simulation results performed in Cadence SPICE environment justify the efficiency of the proposed model.