Design of 8 Bit High Speed Pipelined ADC

Autores

  • Shivani R. Patel Department of VLSI System Design, L. C. Institute of Technology, Bhandu, Gujarat, India
  • Priyesh P. Gandhi Department of VLSI System Design, L. C. Institute of Technology, Bhandu, Gujarat, India

Resumo

High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in many electronic applications. The demand for high-speed, medium resolution, low power ADCs is satisfied by various ADC architectures like folding, flsubranging, pipeline etc. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems.  Pipelined ADC offer attractive combination of high-speed, high-accuracy and low power consumption, which make it the most powerful and efficient data converters among others.This paper describes the implementation of an 8-bit 500 MS/s pipelined ADC using a conventional 0.18 μm CMOS technology in Mentor Graphics Tool. For improving the speed of ADC, Dynamic latch Comparator is used. Two-stage OPAMP topology is used after sample and hold block for improving  settling performance and reduced loading effect in the next stages. It also used in residue amplification, where using proper resistance adjustment gain of exactly two is achieved. The power supply voltage for this pipelined ADC is 1.8 V.The simulation result shows speed achieved with this ADC is 500MHz with input frequency of 1MHz. This ADC consumed power of 169 mW with supply voltage of 1.8 V.  Index Terms- Pipeline, high speed,  ADC, dynamic latch Cite this Article Shivani R. Patel, Priyesh P. Gandhi, Design of 8 Bit High Speed Pipelined ADC, Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 71–80p.

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Publicado

2015-07-02

Edição

Vol. 5 N.º 2 (2015)

Secção

Research Articles

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