卷 6 期 3 (2016)

查看卷 6 期 3 (2016)

出版日期: 2016-10-21

Research Articles

Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy

Shashank Gautam##common.commaListSeparator##Pramod Sharma

1-6
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Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier

Saguna Goel##common.commaListSeparator##Sakshi Bajaj##common.commaListSeparator##Amanpreet Kaur

7-14
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Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers

Akash I. Mecwan##common.commaListSeparator##N M Devashrayee

22-27
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Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform

Pradip C. Bhaskar##common.commaListSeparator##Prachi S. Gosavi

28-34
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A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique

Srinibasa Padhy##common.commaListSeparator##Shivalal Patro##common.commaListSeparator##Monica Swain##common.commaListSeparator##Jitendra Kumar Das

45-55
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Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications

Ankush Chunn##common.commaListSeparator##Rakesh Kumar Sarin

71-87
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VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter

Minakshi Motiram Wanjari##common.commaListSeparator##Pankaj Agrawal##common.commaListSeparator##Ravindra Kshirsagar

88-93
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Review Articles

Design of FPGA Based ALU Using Reversible Logic Gates

Vishal A. Wankhede##common.commaListSeparator##Ramprasad M. Gawande

15-21
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Survey of System-on-Chip Modular Test Approach

Harpreet Vohra##common.commaListSeparator##Amardeep Singh

56-70
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Short Articles

Design of High-Speed and Low-Power Carry Skip Adder

Gutlapalli Venkatrao##common.commaListSeparator##Motkuri Krishna

35-44
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