Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD

Abstract

In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness T_si (20nm); gate oxide thickness T_ox (3nm); buried oxide thickness T_box (200nm) and gate length L_G (60nm). So that maintaining a subthreshold factor, the on/off current ratio, threshold voltage (V_th= 0.5V) and drain induced barrier lowering for a given gate length L_G. Analog performance of device has been investigated interns of g_m, g_ds, A_v, f_t and f_max. All these results have been simulated by using SILVACO TCAD

Keywords:  Index Terms: DG-SOI-MOSFETs, DIBL, and Threshold voltage