Implementation of Variable Random Data Generator

Abstract

Main objective of this paper is to design a hardware model for variable Random data generator module. The random generator module is designed based on the principle of LFSR (linear feedback shift registers). A LFSR is a shift register whose input bit is a linear function of its previous state. The register has a finite number of possible states; it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle. So we should be careful when using this random generator for any cryptographic purposes. The bit positions that affect the next state are called the taps. The maximum period of the cycle over which the sequence repeats is 2^n-1 for a n- bit wide LFSR register. The tap values must be selected carefully for the sequence to attain maximum period. This paper is implementing for different bit width of random numbers with different tapings using  verilog.

Keywords: variable random data generator, maximum period, Taps, LFSR

Cite this Article

Arugonda K, Surender Reddy T. Implementation of Variable Random Data Generator. Journal of Instrumentation Technology and Innovation, 2015; 5(2): 14–18p.