4-Bit Magnitude Comparator Design Using Different Logic Style

Autores

  • Vipul Mittal Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Tanushree . Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Madhulika Arora Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Meenakshi Yadav Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Sakshi Chaudhary Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India

Resumo

 ABSTRACT: 4-bit magnitude comparator using various logic styles is explained in this. Comparison is one of the common arithmetic operation that is used to determine which number is  greater, equal to, or less. Every device from op-amp to Alu needs  to performs comparison operation. At designing level , comparator can be designed using different  logic styles . Here comparison is done for simple 4-Bit combinational comparator and cascaded comparator. Results for  different designs is presented in form of  simulations that is performed on Cadence virtuoso at 180nm technology .    Keywords –– comparator, arithmetic, virtuoso , cascaded Cite this Article Vipul Mittal, Tanushree, Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary. 4-Bit Magnitude Comparator Design Using Different Logic Styles,  Journal of VLSI Design Tools and Technology. 2015; 5 (2):    16–22p.

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Publicado

2015-05-22

Edição

Vol. 5 N.º 2 (2015)

Secção

Research Articles

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