A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

Forfattere

  • M. Hulkey Department of Electronics & Telecommunication Engineering, SRCOE, Pune, Maharashtra, India
  • H. Upadhyay Department of Electronics & Telecommunication Engineering, SRCOE, Pune, Maharashtra, India
  • K. Sujatha Department of Electronics & Telecommunication Engineering, SRCOE, Pune, Maharashtra, India

Nøgleord:

CMOS, Power consumption, Full adder, Ripple carry adder, High performance, Inverter, Adder, Constant delay.

Resumé

  Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style is having two blocks and having a unique characteristic at which we get pre-evaluated output. But the new proposed modified constant logic style and clocked logic style provides better result than the constant logic style. The CMOS technology is used for the simulation process by which the parameter of power is measured which is compared with constant delay logic style.   Keywords: CMOS, power consumption, full adder, ripple carry adder, high performance, inverter, adder, constant delay Cite this ArticleM. Hulkey, H. Upadhyay, K. Sujatha. A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit. Journal of VLSI Design Tools and Technology. 2016; 6(1): 1–5p.

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Publiceret

2016-01-20

Nummer

Årg. 6 Nr. 1 (2016)

Sektion

Research Articles

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