Årg. 6 Nr. 1 (2016)

Se Årg. 6 Nr. 1 (2016)

Publiceret: 2016-01-20

Research Articles

A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

M. Hulkey, H. Upadhyay, K. Sujatha

1-5
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Hardware Implementation of Configurable Multi Image Fusion

SS. Malwadkar, WM. Mendre, SS. Agrawal

6-15
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Simulation Study of Tapered Shape FinFET

G. Musalgaonkar, A. Shrivastava, S. Singh, A. Acharya

21-31
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Switched Capacitor Based RC Filter

Jinal A. Prajapati, Prof. Mehul L. Patel

32-40
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Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell

P. Raikwal, V. Neema, A. Verma

41-48
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence

J. K. Arya, A. Raman

49-54
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-Simulation

Bhupendra Fataniya, Akash Mecwan, Dhaval Shah

55-61
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Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology

Herman Al Ayubi, Navaid Z. Rizvi, Piyush K. Mishra

62-72
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology

Jubal Saji, Shoaib Kamal

77-78
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A Differentiator Based on Second Generation Current Controlled Conveyor

A. Kumar, R. Pandey

89-95
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Review Articles

A Review for Power Optimization in MOS Devices using Different Logic Styles

M. Hulkey, H. Upadhyay, K. Sujatha

16-20
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell

Jitendra Krishna Arya, Ashish Raman

73-77
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